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Difference between revisions of "EclipseLink/Examples/JPA/Simulation"
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| − | =Simulation JPA Application Example= | + | <!--=Simulation JPA Application Example= |
| + | <div style="border: 3px red solid;" align="center" ><font color="red">DISCLAIMER: This page reflects investigation into how EclipseLink technology can used as part of - or benefit from integration with other projects. It does NOT imply any formal certification from EclipseLink on these technologies or make any assumptions on the direction of the API. This page is purely experimental speculation.</font></div> | ||
==Purpose== | ==Purpose== | ||
| − | *This sumulation will serve as a ''near real world'' enterprise application that showcases utilizing JPA as the persistence or integration layer - specifically using [http://wiki.eclipse.org/EclipseLink/Examples/JPA EclipseLink JPA] as the provider. | + | *This sumulation will serve as a <font color="blue">''near real world''</font> '''enterprise application''' that showcases utilizing '''JPA''' as the persistence or integration layer of a major hardware/software system application - specifically using '''[http://wiki.eclipse.org/EclipseLink/Examples/JPA EclipseLink JPA]''' as the JPA provider. |
| − | *The software will also showcase the distributed performance capabilities of EclipseLink by using the 1st level cache and an optional 2nd level distributed memory cache in clustered mode. | + | *The software will also showcase the distributed performance capabilities of EclipseLink by using the 1st level cache and an optional 2nd level distributed memory cache in clustered mode using either '''TopLink Grid''' or '''Terracotta EhCache'''. |
*Additionally, the process and result of this analysis will use and showcase an example UML based design approach. | *Additionally, the process and result of this analysis will use and showcase an example UML based design approach. | ||
| − | *This enterprise application will offer the services of a simulated | + | *This enterprise application will offer the services of a simulated '''SIMD Parallel Processor''' somewhat like the Connection Machine ''(Ref: [http://en.wikipedia.org/wiki/Connection_Machine Thinking Machines CM-2], MIT Cosmic Cube (MIMD), Burroughs Illiac IV etc.)''. |
**Why are we choosing an older architecture to simulate? | **Why are we choosing an older architecture to simulate? | ||
| − | ***a) The architecture is very clean and even though it is very large - is simple enough to implement. | + | ***a) The architecture is very clean and '''closed''' and even though it is very large - is simple enough to implement. |
| − | ***b) The Design by Danny Hillis in his dissertation is out of print as of 2005 and Thinking Machines no longer exists in whole but was partially acquired by Oracle - so we are free to simulate the device. | + | ***b) The Design by Danny Hillis in his dissertation is out of print as of 2005 and Thinking Machines no longer exists in whole but was partially acquired by Oracle - so we are free to simulate the device in ''software'' and ''hardware''. |
| − | ***b) The design is proven and static - as it has been superceeded by more powerfull designs). | + | ***b) The design is proven and static - as it has been superceeded by and incorporated in more powerfull designs). |
| − | ***c) The massively parallel processing design of the [http://en.wikipedia.org/wiki/Connection_Machine CM-2] matches our goal of utilizing parallelism at both the thread and multi-core processor level on our host machine. | + | ***c) The massively parallel processing design of the [http://en.wikipedia.org/wiki/Connection_Machine CM-2] matches our goal of utilizing parallelism at both the thread and multi-core processor level on our plain host machine - an 8 core Intel i7-920 - although at a more granular level. |
===Goals=== | ===Goals=== | ||
*We would like to explore the following limits of the JPA provider and hosting application server. | *We would like to explore the following limits of the JPA provider and hosting application server. | ||
| − | **Performance and Volumetrics: We require 65536 processor objects. | + | **Performance and Volumetrics: We require 65536 processor objects - but will likely simulate a Kilo (1024) core machine. |
==Infrastructure== | ==Infrastructure== | ||
| − | *OS: Windows | + | *OS: Windows 7 64 bit |
| − | *Database: | + | *Database: Derby 10.5.3.0 |
| − | *JPA provider: [http://www.eclipselink.org EclipseLink | + | *JPA provider: [http://www.eclipselink.org EclipseLink 2.2] |
| − | *JDK: Sun 1.6. | + | *JDK: Sun 1.6.0_17 |
==Analysis== | ==Analysis== | ||
| − | ===Data Model=== | + | ===Data Model 1: Dynamic Routing Hypercube=== |
| − | ====Processor Architecture==== | + | ====Processor Architecture 1: Finite Element Space==== |
| − | *Each CM-2 processor is composed of up to '''64k (65536)''' 1-bit processors arranged in a 12-dimensional hypercube. | + | *Each CM-2 processor is composed of up to '''64k (65536)''' 1-bit processors arranged in a 12-dimensional hypercube of 16 processors per node. |
| − | **There are '''16''' 1-bit | + | **There are '''16''' 1-bit cores per chip along with '''1''' routing core per chip. |
***There are '''32''' cpu chips and '''32''' ram chips per backplane board | ***There are '''32''' cpu chips and '''32''' ram chips per backplane board | ||
****There are '''16''' boards per quadrant | ****There are '''16''' boards per quadrant | ||
*****There are '''8''' quadrands to a CM-2 | *****There are '''8''' quadrands to a CM-2 | ||
| − | **We therefore have '''(2^4=16) x (2^5=32) x (2^4=16) x (2^3=8) = 2^16 = 65536''' possible | + | **We therefore have '''(2^4=16) x (2^5=32) x (2^4=16) x (2^3=8) = 2^16 = 65536''' possible cores in a fully configured system. |
| − | + | ====Static Class Hierarchy==== | |
| + | *Hypercube (quadrants(1:M), input, output, program) | ||
| + | *Quadrant (boards(1:M), hypercube(1:1)) | ||
| + | *Board (processorChips(1:M), ramChips(1:M)) | ||
| + | *''Chip(A)'' | ||
| + | **ProcessorChip (processors (1:M), router (1:1)) | ||
| + | **MemoryChip | ||
| + | *''Processor(A)'' | ||
| + | **VectorProcessor(alu, stateMachine, uProgram) | ||
| + | **RouterProcessor (routers(1:M)) | ||
| + | ===Data Model 2: Static Routing Planar Array=== | ||
| + | ====Processor Architecture 2: Cellular Automata==== | ||
| + | *Each CAS processor is composed of an open number of 1 bit processors arranged in a rectangular grid either bounded or toroidal. Here will will simulate a minimum '''44''' x '''24''' array of '''1056''' cores so we can fit a minimum size ''Gosper glider gun'''. | ||
| + | **There are '''8''' 1-bit cores per chip - each core manages its own nearest neighboor routing | ||
| + | ***The chips are arranged logically in a '''44''' x '''24''' grid totalling '''1056''' cores (a Kilocore). | ||
====Static Class Hierarchy==== | ====Static Class Hierarchy==== | ||
*Hypercube (quadrants(1:M), input, output, program) | *Hypercube (quadrants(1:M), input, output, program) | ||
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==Design== | ==Design== | ||
| − | ===JPA Data Model=== | + | ===Software=== |
| − | ====Board.java==== | + | ====JPA Data Model==== |
| + | ===Hardware=== | ||
| + | ====Block Diagrams==== | ||
| + | =====Prototype Three Dimensional Hypercube===== | ||
| + | *The following diagram illustrates via block diagram the layout of a prototype 3 dimensional hypercube architecture at the bottom hardware end of the implementation stack where '''[http://www.eclipselink.org EclipseLink]''' acts as the '''ORM''' persistence layer for both the design and runtime parts of the system. | ||
| + | |||
| + | [[Image:Prop_3hypercube.jpg]] | ||
| + | =====Prototype Planar SIMD Array===== | ||
| + | *The following diagrams discuss design issues surrounding a 2 dimensional array of processing module cores - their layout, connection topology and synchronization protocols. | ||
| + | ======Design Issue 1: Minimizing Inter-module Connections====== | ||
| + | *The following 2 x 8 layout of 2 chips of 8 cores forming a 16 core module is ''not optimum''. | ||
| + | [[Image:PropCAS_16core_module_suboptimum_2x8_config_v20100907.jpg]] | ||
| + | *The following 4 x 4 layout of 2 chips of 8 cores forming a 16 core module is ''optimum''. | ||
| + | [[Image:PropCAS_16core_module_optimum_4x4_config_v20100907.jpg]] | ||
| + | *We can reduce the 8 connection paths to 4 by ''reusing'' the corner values of the '''NEWS''' primary connectors - which is only required for the incoming connections - not the outgoing ones. | ||
| + | [[Image:PropCAS_16core_module_ext_connect_block_v20100907.jpg]] | ||
| + | |||
| + | ====Schematics==== | ||
| + | |||
| + | ==Implementation== | ||
| + | ===Software=== | ||
| + | ====Business Logic Client==== | ||
| + | ====Schema Model==== | ||
| + | =====Board.java===== | ||
<source lang="java"> | <source lang="java"> | ||
@Entity | @Entity | ||
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</source> | </source> | ||
| − | ====Chip.java==== | + | =====Chip.java===== |
<source lang="java"> | <source lang="java"> | ||
@MappedSuperclass | @MappedSuperclass | ||
| Line 110: | Line 148: | ||
private Board board; | private Board board; | ||
</source> | </source> | ||
| − | ====Hypercube.java==== | + | =====Hypercube.java===== |
<source lang="java"> | <source lang="java"> | ||
@Entity | @Entity | ||
| Line 140: | Line 178: | ||
} | } | ||
</source> | </source> | ||
| − | ====Processor.java==== | + | =====Processor.java===== |
<source lang="java"> | <source lang="java"> | ||
@MappedSuperclass | @MappedSuperclass | ||
| Line 157: | Line 195: | ||
private Integer id; | private Integer id; | ||
</source> | </source> | ||
| − | ====ProcessorChip.java==== | + | =====ProcessorChip.java===== |
<source lang="java"> | <source lang="java"> | ||
@Entity | @Entity | ||
| Line 188: | Line 226: | ||
</source> | </source> | ||
| − | ====Quadrant.java==== | + | =====Quadrant.java===== |
<source lang="java"> | <source lang="java"> | ||
@Entity | @Entity | ||
| Line 226: | Line 264: | ||
} | } | ||
</source> | </source> | ||
| − | ====VectorProcessor.java==== | + | =====VectorProcessor.java===== |
<source lang="java"> | <source lang="java"> | ||
@Entity | @Entity | ||
| Line 239: | Line 277: | ||
</source> | </source> | ||
| − | ====CM2Console.java==== | + | =====CM2Console.java===== |
*This is a minimum Java SE JPA client | *This is a minimum Java SE JPA client | ||
| Line 432: | Line 470: | ||
</source> | </source> | ||
| − | = | + | ====Persistence Unit==== |
| − | + | ||
| − | ===Persistence Unit=== | + | |
<source lang="xml"> | <source lang="xml"> | ||
<?xml version="1.0" encoding="UTF-8"?> | <?xml version="1.0" encoding="UTF-8"?> | ||
| Line 453: | Line 489: | ||
<property name="eclipselink.jdbc.user" value="scott"/> | <property name="eclipselink.jdbc.user" value="scott"/> | ||
<property name="eclipselink.jdbc.password" value="pw"/> | <property name="eclipselink.jdbc.password" value="pw"/> | ||
| − | |||
<property name="eclipselink.ddl-generation" value="drop-and-create-tables"/> | <property name="eclipselink.ddl-generation" value="drop-and-create-tables"/> | ||
<property name="eclipselink.ddl-generation.output-mode" value="database"/> | <property name="eclipselink.ddl-generation.output-mode" value="database"/> | ||
| Line 460: | Line 495: | ||
</persistence> | </persistence> | ||
</source> | </source> | ||
| + | ===Hardware=== | ||
| + | ====Bill Of Materials==== | ||
==Testing== | ==Testing== | ||
| Line 476: | Line 513: | ||
==Appendices== | ==Appendices== | ||
| + | ===Software Design Issues=== | ||
| + | ===Hardware Design Issues=== | ||
| + | ====DI 1: Can we bootstrap the last cog to run assembly==== | ||
| + | *In order to run true SIMD on the matrix in assembly as well as SPIN, we need a way to reload cog0 with assembly like wa are able to do with cogs 1-7 and discard the bytecode interpreter in cog0 | ||
| + | |||
==References== | ==References== | ||
| + | *[[EclipseLink/Building/64bit#310662:_StackOverflowError_for_64_linked_entities_in_6_dimensional_hypercube_network|Limitations of the Heap on 64 bit machines]] | ||
*[http://eclipsejpa.org Other JPA examples] | *[http://eclipsejpa.org Other JPA examples] | ||
| + | --> | ||