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Difference between revisions of "EclipseLink/Examples/JPA/Simulation"
< EclipseLink | Examples | JPA
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| − | =Simulation JPA Application Example= | + | <!--=Simulation JPA Application Example= |
<div style="border: 3px red solid;" align="center" ><font color="red">DISCLAIMER: This page reflects investigation into how EclipseLink technology can used as part of - or benefit from integration with other projects. It does NOT imply any formal certification from EclipseLink on these technologies or make any assumptions on the direction of the API. This page is purely experimental speculation.</font></div> | <div style="border: 3px red solid;" align="center" ><font color="red">DISCLAIMER: This page reflects investigation into how EclipseLink technology can used as part of - or benefit from integration with other projects. It does NOT imply any formal certification from EclipseLink on these technologies or make any assumptions on the direction of the API. This page is purely experimental speculation.</font></div> | ||
==Purpose== | ==Purpose== | ||
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====JPA Data Model==== | ====JPA Data Model==== | ||
===Hardware=== | ===Hardware=== | ||
| − | ====Prototype | + | ====Block Diagrams==== |
| + | =====Prototype Three Dimensional Hypercube===== | ||
*The following diagram illustrates via block diagram the layout of a prototype 3 dimensional hypercube architecture at the bottom hardware end of the implementation stack where '''[http://www.eclipselink.org EclipseLink]''' acts as the '''ORM''' persistence layer for both the design and runtime parts of the system. | *The following diagram illustrates via block diagram the layout of a prototype 3 dimensional hypercube architecture at the bottom hardware end of the implementation stack where '''[http://www.eclipselink.org EclipseLink]''' acts as the '''ORM''' persistence layer for both the design and runtime parts of the system. | ||
[[Image:Prop_3hypercube.jpg]] | [[Image:Prop_3hypercube.jpg]] | ||
| − | ====Prototype | + | =====Prototype Planar SIMD Array===== |
*The following diagrams discuss design issues surrounding a 2 dimensional array of processing module cores - their layout, connection topology and synchronization protocols. | *The following diagrams discuss design issues surrounding a 2 dimensional array of processing module cores - their layout, connection topology and synchronization protocols. | ||
| − | =====Design Issue 1: Minimizing Inter-module Connections===== | + | ======Design Issue 1: Minimizing Inter-module Connections====== |
*The following 2 x 8 layout of 2 chips of 8 cores forming a 16 core module is ''not optimum''. | *The following 2 x 8 layout of 2 chips of 8 cores forming a 16 core module is ''not optimum''. | ||
[[Image:PropCAS_16core_module_suboptimum_2x8_config_v20100907.jpg]] | [[Image:PropCAS_16core_module_suboptimum_2x8_config_v20100907.jpg]] | ||
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*We can reduce the 8 connection paths to 4 by ''reusing'' the corner values of the '''NEWS''' primary connectors - which is only required for the incoming connections - not the outgoing ones. | *We can reduce the 8 connection paths to 4 by ''reusing'' the corner values of the '''NEWS''' primary connectors - which is only required for the incoming connections - not the outgoing ones. | ||
[[Image:PropCAS_16core_module_ext_connect_block_v20100907.jpg]] | [[Image:PropCAS_16core_module_ext_connect_block_v20100907.jpg]] | ||
| + | |||
| + | ====Schematics==== | ||
==Implementation== | ==Implementation== | ||
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<property name="eclipselink.jdbc.user" value="scott"/> | <property name="eclipselink.jdbc.user" value="scott"/> | ||
<property name="eclipselink.jdbc.password" value="pw"/> | <property name="eclipselink.jdbc.password" value="pw"/> | ||
| − | |||
<property name="eclipselink.ddl-generation" value="drop-and-create-tables"/> | <property name="eclipselink.ddl-generation" value="drop-and-create-tables"/> | ||
<property name="eclipselink.ddl-generation.output-mode" value="database"/> | <property name="eclipselink.ddl-generation.output-mode" value="database"/> | ||
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==Appendices== | ==Appendices== | ||
| + | ===Software Design Issues=== | ||
| + | ===Hardware Design Issues=== | ||
| + | ====DI 1: Can we bootstrap the last cog to run assembly==== | ||
| + | *In order to run true SIMD on the matrix in assembly as well as SPIN, we need a way to reload cog0 with assembly like wa are able to do with cogs 1-7 and discard the bytecode interpreter in cog0 | ||
| + | |||
==References== | ==References== | ||
*[[EclipseLink/Building/64bit#310662:_StackOverflowError_for_64_linked_entities_in_6_dimensional_hypercube_network|Limitations of the Heap on 64 bit machines]] | *[[EclipseLink/Building/64bit#310662:_StackOverflowError_for_64_linked_entities_in_6_dimensional_hypercube_network|Limitations of the Heap on 64 bit machines]] | ||
*[http://eclipsejpa.org Other JPA examples] | *[http://eclipsejpa.org Other JPA examples] | ||
| + | --> | ||